Typically, known data processors comprise a microsequencer and an execution unit. Data operations are performed in the execution unit, which typically comprises an arithmetic unit, registers, buses, and a data shifter. Generally, the microsequencer is either `hardwired`, i.e. designed using combinatorial logic gates, or `microcoded`, i.e. designed using a programmable memory. In a microcoded design, the user visible `macroinstruction` of the data processor is executed by one or several microinstructions. These microinstructions control the execution unit so as to perform the function of the macroinstruction. A sequence of microinstructions, referred to as a microroutine or a microprogram, may be necessary in order to execute a complex macroinstruction.
In a typical pipelined data processor, macroinstructions are "fetched" from a main memory and stored in an instruction pipeline (PIPE) made up of "instruction registers" (IRs). The PIPE is structured such that instructions enter at one end, and the values are shifted toward the other end where they are used and then discarded. Instruction decode logic (often a programmable logic array (PLA)) accesses the instructions in the pipe and "decodes" the macroinstruction. This "decode" provides the initial microstore address of the microroutine that is to be used to perform the particular macroinstruction. At the conclusion of a microroutine, the microinstruction will request another instruction decode to determine which microroutine to execute next. This instruction decode may be a further decode of the same macroinstruction word, a decode of additional words of a multiword macroinstruction, or a decode of a new macroinstruction.
An advantage of microcode design is that the microsequencer architecture is simpler and more straight-forward, and the microsequences can be easily modified by reprogramming the memory. The memory which stores the microcode is referred to as the microstore, and is often implemented as read-only-memory (ROM), or as read/write, random access memory (RAM). Generally, the ROM is divided up into two portions, a nanoROM portion (nanoROM), which provides control information to the execution unit, and a microROM portion (microROM) which provides the next nanoROM address during instruction sequencing. Typically, an entry point PLA provides the initial nanoROM address, which is saved in the nanoROM address latch herein referred to as a microprogram counter (uPC). Typically, the microsequencer requires a separate unique address bus for both the microROM and entry point PLA, and a multiplexor to select the appropriate source of the nanoROM address stored in the uPC. The use of two separate and unique address buses requires additional silicon area, and is therefore, expensive to implement. Furthermore, the use of two separate and unique address buses may result in bottlenecks in the routing from one physical location to the other.